73. SR Latch

How do you plan to solve it?

module sr_latch_nor (
    input  S,
    input  R,
    output Q,
    output Qn
);
    // Write your code here
    wire [1:0] sel;
    assign sel = {S,R};
    reg temp,tempn;
    always @* begin
        case(sel)
        2'd0 : begin temp = temp; tempn = tempn; end
        2'd1 : begin temp = 0; tempn = 1; end
        2'd2 : begin temp = 1; tempn = 0; end
        2'd3 : begin temp = 0; tempn = 1; end
        endcase
    end
    assign Q = temp;
    assign Qn = tempn;
endmodule