73. SR Latch

How do you plan to solve it?

module sr_latch_nor (
    input  S,
    input  R,
    output Q,
    output Qn
);
    // Write your code here
    reg Q_reg , Qn_reg;
    
    always@(*)begin
        if((S && R) | (!S && R)) 
        begin
            Q_reg = 1'b0;
            Qn_reg = 1'b1;
        end else if( S && !R)
        begin
            Q_reg = 1'b1;
            Qn_reg = 1'b0;
        end 
        end 
        assign Q= Q_reg;
        assign Qn = Qn_reg;
endmodule