73. SR Latch

How do you plan to solve it?

module sr_latch_nor (
    input  S,
    input  R,
    output reg Q,
    output reg Qn
);
    // Write your code here\
    reg prev_Q;
    always @* begin
        if (R == 1) begin
            Q <= 1'b0;
            prev_Q <= Q;
        end else if (S == 1) begin
            Q <= 1'b1;
            prev_Q <= Q;
        end else if (S == 0) begin
            Q <= prev_Q;
        end

        Qn <= ~Q;
    end
endmodule