73. SR Latch

How do you plan to solve it?

module sr_latch_nor (
    input  S,
    input  R,
    output Q,
    output Qn
);
    // Write your code here
    reg Q_r, Qn_r;
    wire [1:0] SR = {S,R};
    
    always @(*) begin
        if((SR == 2'b01) || (SR == 2'b11)) begin
            Q_r = 1'b0;
        end else if((SR == 2'b10)) begin
            Q_r = 1'b1;
        end

        Qn_r = ~Q_r;
    end

    assign Q = Q_r;
    assign Qn = Qn_r;   
endmodule