73. SR Latch

How do you plan to solve it?

module sr_latch_nor (
    input  wire S,
    input  wire R,
    output reg  Q,
    output wire Qn
);

    // Complement output must always match Q
    assign Qn = ~Q;

    always @(*) begin
        case ({S,R})
            2'b10: Q = 1'b1;   
            2'b01: Q = 1'b0;   
            2'b11: Q = 1'b0;   
            2'b00: ;           
        endcase
    end

endmodule