73. SR Latch

How do you plan to solve it?

module sr_latch_nor (
    input  wire S,
    input  wire R,
    output reg  Q,
    output wire Qn
);

//
// Active-high SR latch
// Deterministic handling:
// S=1,R=1 -> Reset
//

always @(*) begin

    // Reset dominates
    if (R) begin
        Q = 1'b0;
    end

    // Set
    else if (S) begin
        Q = 1'b1;
    end

    // Hold condition:
    // S=0, R=0
    // No assignment -> latch inferred
end

// Complement output
assign Qn = ~Q;

endmodule