73. SR Latch

How do you plan to solve it?

module sr_latch_nor (
    input  S,
    input  R,
    output reg Q,
    output reg Qn
);
    // Write your code here
    always @(*) begin
        if (S&&~R) begin
            Q=1'b1;
            Qn=1'b0;
        end 
        else if (~S&&R) begin
            Q=1'b0;
            Qn=1'b1;
        end
        else if (S&&R) begin
            Q=1'b0;
            Qn=1'b1;
        end
    end
    
    
endmodule