73. SR Latch

How do you plan to solve it?

module sr_latch_nor (
    input  S,
    input  R,
    output Q,
    output Qn
);
    // Write your code here
    wire nR, S_eff;

    not u_invR(nR, R);           // nR = ~R
    and u_setg(S_eff, S, nR);    // S_eff = S & ~R  (suppress set when R=1)

    nor uQ (Q , R    , Qn);      // Q  = ~(R | Qn)
    nor uQn(Qn, S_eff, Q );
endmodule