73. SR Latch

How do you plan to solve it?

module sr_latch_nor (
    input  S,
    input  R,
    output reg Q,
    output reg Qn
);
    // Write your code here
    //wire Q,Qn;
    always@(*)begin
    if (S==1 && R ==0)begin
        Q <= 1'b1;
        Qn <= 1'b0;
    end
    else if (S==0 && R ==1)begin
         Q <= 1'b0;
         Qn <= 1'b1;
    end
    else if (S==0 && R ==0)begin
         Q <= Q;
         Qn <= Qn;
    end
     else if (S==1 && R ==1)begin
         Q <= 1'b0;
         Qn <= 1'b1;
    end
    end
    
endmodule