73. SR Latch

How do you plan to solve it?

module sr_latch_nor (
    input  S,
    input  R,
    output Q,
    output Qn
);
    // Write your code here
    reg Q_r, Qn_r;
    always @ (*) begin
        if (S && R) begin
            Q_r = 1'b0;
            Qn_r = 1'b1;
        end else if (S && !R) begin
            Q_r = 1'b1;
            Qn_r = 1'b0;
        end else if (!S && R) begin
            Q_r = 1'b0;
            Qn_r = 1'b1;
        end
    end

    assign Q = Q_r;
    assign Qn = Qn_r;

    
endmodule