73. SR Latch

How do you plan to solve it?

module sr_latch_nor (
    input  S,
    input  R,
    output reg Q,
    output reg Qn
);
    always @* begin
        if ((S == 1'b1) && (R == 1'b0)) begin
            Q = 1'b1;
        end
        if (R == 1'b1) begin
            Q = 1'b0;
        end
        Qn = ~Q;
    end
    
endmodule