73. SR Latch

How do you plan to solve it?

module sr_latch_nor (
    input  S,
    input  R,
    output Q,
    output Qn
);
    // Write your code here
    // wire s, r;
    // not n1 ( r, R );
    // and a1 ( s, S, r );
    // nor n2 ( Q, R, Qn );
    // nor n3 ( Qn, Q, s);
    reg q;
    always @(*) begin
        case({S,R})
            2'b00: q = Q;
            2'b01: q = 1'b0;
            2'b10: q = 1'b1;
            2'b11: q = 1'b0;
        endcase
    end
    assign Q = q;
    assign Qn = ~Q;
endmodule