73. SR Latch

How do you plan to solve it?

module sr_latch_nor (
    input  S,
    input  R,
    output Q,
    output Qn
);
    // Write your code here
    wire no_r, and_sr;

    // always @* begin
        not not_r(no_r, R);
        and and_snr(and_sr, S, no_r);
        nor q_r_qn(Q, R, Qn);
        nor qn_and_sr_q(Qn, and_sr, Q);
    // end
    
endmodule