How do you plan to solve it?
module sr_latch_nor ( input S, input R, output reg Q, output Qn ); // Write your code here assign Qn=~Q; always@(*)begin case({S,R}) 2'b10 :Q= 1'b1;//set 2'b01 :Q= 1'b0;//reset 2'b00 :Q= Q ;//hold 2'b11 :Q= 1'b0;// endcase end endmodule