73. SR Latch

How do you plan to solve it?

module sr_latch_nor (
    input  S,
    input  R,
    output Q,
    output Qn
);
    // Write your code here
   reg Qn_reg;
   reg Q_reg;
always @(*)
begin
if(S && !R)begin
    Qn_reg=1'b0;
    Q_reg=1'b1;   //set
end else if(!S && R)begin
    Qn_reg=1'b1; //reset
    Q_reg=1'b0;
end else if(S && R)begin
    Qn_reg=1'b1; //reset dominate
    Q_reg=1'b0;
end
end
assign Qn=Qn_reg;
assign Q=Q_reg;

endmodule