73. SR Latch

How do you plan to solve it?

module sr_latch_nor (
    input  S,
    input  R,
    output Q,
    output Qn
);
    // Write your code here
    reg q,qn;
    always @(*)begin
        if(S && R)begin q <= 0; qn <= 1;end 
        else if (S && ~R)begin q <= 1; qn <= 0;end
        else if (~S && R)begin q <= 0; qn <= 1;end
    end
    assign Q = q;
    assign Qn = qn;
endmodule