10. Splitting Vector

Design a Verilog module called vector_splitter that takes an 8-bit input vector and divides it into:

out1 → upper 4 bits (4-bit output)
out2 → next 2 bits (2-bit output)
out3 → bit 1 (1-bit output)
out4 → bit 0 (1-bit output)

Requirements

Module name: vector_splitter
Input: in_vec[7:0]
Outputs:
- out1[3:0] = bits [7:4]
- out2[1:0] = bits [3:2]
- out3 = bit [1]
- out4 = bit [0]

Notes

You must use vector indexing ([msb:lsb]) and bit-select ([i]) operators.
Do not use concatenation or shift operators to implement outputs.
Trick: Make sure outputs are in correct order — e.g., out2[1:0] should map to [3:2] in the same order, not reversed.

Expected behavior (example)

If in_vec = 8'b1101_0110 (binary = 0xD6):

out1 = 1101 (bits [7:4])
out2 = 01 (bits [3:2])
out3 = 1 (bit [1])
out4 = 0 (bit [0])

Please login to run the code.

Testbench Code

`timescale 1ns/1ps

module tb_vector_splitter;
    // Input
    reg [7:0] in_vec;

    // DUT outputs
    wire [3:0] out1;
    wire [1:0] out2;
    wire       out3;
    wire       out4;

    // Expected outputs
    reg [3:0] expected_out1;
    reg [1:0] expected_out2;
    reg       expected_out3;
    reg       expected_out4;

    // Mismatch signal (true if any output mismatches expected)
    wire mismatch = (out1 !== expected_out1) ||
                    (out2 !== expected_out2) ||
                    (out3 !== expected_out3) ||
                    (out4 !== expected_out4);

    integer TOTAL_TEST_CASES = 0;
    integer TOTAL_PASSED_TEST_CASES = 0;
    integer TOTAL_FAILED_TEST_CASES = 0;

    // Instantiate DUT
    vector_splitter dut (
        .in_vec(in_vec),
        .out1(out1),
        .out2(out2),
        .out3(out3),
        .out4(out4)
    );

    // VCD dump
    initial begin
        $dumpfile("tb_vector_splitter.vcd");
        $dumpvars(0,
            tb_vector_splitter.in_vec,
            tb_vector_splitter.out1, tb_vector_splitter.out2, tb_vector_splitter.out3, tb_vector_splitter.out4,
            tb_vector_splitter.expected_out1, tb_vector_splitter.expected_out2, tb_vector_splitter.expected_out3, tb_vector_splitter.expected_out4,
            tb_vector_splitter.mismatch
        );
    end

    // Task to run one test
    task run_test;
        input [7:0] t_in;
        begin
            in_vec = t_in;

            // Expected outputs
            expected_out1 = t_in[7:4];
            expected_out2 = t_in[3:2];
            expected_out3 = t_in[1];
            expected_out4 = t_in[0];

            #1;
            TOTAL_TEST_CASES++;
            if (!mismatch) begin
                TOTAL_PASSED_TEST_CASES++;
            end else begin
                TOTAL_FAILED_TEST_CASES++;
                $display("FAILED: in_vec=%b | out1=%b out2=%b out3=%b out4=%b | expected=%b %b %b %b | mismatch=%b",
                          in_vec, out1, out2, out3, out4,
                          expected_out1, expected_out2, expected_out3, expected_out4, mismatch);
            end
        end
    endtask

    initial begin
        // Test cases
        run_test(8'b0000_0000);
        run_test(8'b1111_1111);
        run_test(8'b1101_0110); // tricky case from example
        run_test(8'b1010_1100);
        run_test(8'b0101_0011);

        // Summary
        $display("======================================");
        $display("TOTAL_TEST_CASES=%0d", TOTAL_TEST_CASES);
        $display("TOTAL_PASSED_TEST_CASES=%0d", TOTAL_PASSED_TEST_CASES);
        $display("TOTAL_FAILED_TEST_CASES=%0d", TOTAL_FAILED_TEST_CASES);
        $display("ALL_TEST_CASES_PASSED=%s",
                 (TOTAL_FAILED_TEST_CASES==0) ? "true" : "false");
        $display("======================================");

        $finish;
    end
endmodule