11. Vector Concatenation

How do you plan to solve it?

The module uses Verilog’s concatenation operator to pack several input signals of different widths into an 8-bit output vector, combining multi-bit buses and single-bit controls into a compact and efficient wiring-only design.

Uses Verilog’s concatenation operator {} to pack the inputs into the output vector in a specific bit order:

• A contributes 4 bits (A[3:0])
• B contributes 2 bits (B[1:0])
• !C contributes 1 bit (logical inversion of C)
• D contributes 1 bit

The concatenation places the signals from left to right, filling OUT[7:0] from the most significant bit to the least significant bit.

/*Write your code here*/
module concat8_packer(
    input [3:0] A,
    input [1:0] B,
    input C,
    input D,
    output [7:0] OUT
);
    assign OUT = {A,B,!C,D};
endmodule