11. Vector Concatenation

How do you plan to solve it?

/*Write your code here*/
module concat8_packer(input[3:0] A,input[1:0] B, input C,D,output[7:0] OUT);
wire  not_c;
assign not_c=~C;
assign OUT[7:2]={A[3:0],B[1:0]};
assign OUT[1]=not_c;
assign OUT[0]=D;
endmodule