11. Vector Concatenation

How do you plan to solve it?

module concat8_packer (
    input  [3:0] A,
    input  [1:0] B,
    input        C,
    input        D,
    output [7:0] OUT
);
    assign OUT[7:4] = A;     // Bits [7:4] = A[3:0]
    assign OUT[3:2] = B;     // Bits [3:2] = B[1:0]
    assign OUT[1]   = ~C;    // Bit [1] = bitwise NOT of C
    assign OUT[0]   = D;     // Bit [0] = D
endmodule