11. Vector Concatenation

How do you plan to solve it?

module concat8_packer (input [3:0]A,
                       input [1:0]B,
                       input C,D,
                       output [7:0]OUT);
/*In Verilog, there are two different things:
1.Packed array (vector)
2.Unpacked array (memory-style)

These are NOT the same
Here we used unpacked array
if we were using packed array we would declare like a[3:0]*/
assign OUT = {A,B,~C,D};



endmodule