11. Vector Concatenation

How do you plan to solve it?

Since there was no need of changing the order of MSB and LSB in inputs while assigning it,
we can directly write 
assign OUT = {A, B, ~C, D}; 
instead of 
assign OUT = {A[3:0], B[1:0], ~C, D};

module concat8_packer(
    input wire [3:0]  A,
    input wire [1:0]  B,
    input wire        C,
    input wire        D,
    output wire [7:0] OUT
);
    
    // assign OUT [7:4] = A[3:0];
    // assign OUT [3:2] = B [1:0];
    // assign OUT [1]   = ~C;
    // assign OUT [0]   = D;

    assign OUT = {A,B,~C,D};    

endmodule