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7. XOR Gate

module top_module(input a, input b, output y);
  assign y = a ^ b;
endmodule

💡 Remember

  • The ^ operator in Verilog performs bitwise XOR.
  • Output is 1 only when inputs differ (a=0,b=1 or a=1,b=0).
  • Synthesizes to a single XOR gate in hardware.