87. 4-bit Bidirectional Shift Register

Design a 4-bit bidirectional shift register with asynchronous active-high reset. On each rising edge of CLK (when not in reset), the register shifts left or right depending on DIR, inserting the new serial_in bit.

Requirements

• Module: shift_reg_bidirectional
• Ports:
  • Inputs:
    • CLK
    • RST
    • DIR
    • serial_in
  • Outputs:
    • Q[3:0]
• Functional behavior
  • RST=1 (any time) → Q=4'b0000.
  • On posedge CLK with RST=0:
    • DIR=1 → shift left: Q <= {Q[2:0], serial_in}.
    • DIR=0 → shift right: Q <= {serial_in, Q[3:1]}.
  • Use nonblocking assignments (<=).