86. 4-bit Register with Synchronous Reset

Design a 4-bit positive-edge–triggered register that loads D[3:0] on the rising edge of CLK. If RST=1 at the edge, the register synchronously clears to 0000.

Requirements

• Module: reg4_sync_reset
• Ports:
  • Inputs:
    • CLK
    • RST
    • D[3:0]
  • Outputs:
    • Q[3:0]
• Functional behavior
  • On posedge CLK with RST=1 → Q=0000
  • On posedge CLK with RST=0 → Q=D
  • Between edges → hold