88. Parallel-In Serial-Out Register

Design a 4-bit PISO register that loads D[3:0] when LOAD=1 and then shifts the word out LSB-first on each rising edge while LOAD=0. The internal shift register resets asynchronously to zero. On the load edge, serial_out must not output the LSB (no repetition); streaming begins on the next clock edge after LOAD is deasserted.

Requirements

• Module: piso4
• Ports:
  • Inputs:
    • CLK
    • RST
    • LOAD
    • D[3:0]
  • Outputs:
    • serial_out
• Functional behavior
  • RST=1 (any time): internal SR = 0, serial_out = 0.
  • On posedge CLK with RST=0:
    • If LOAD=1: capture D into SR; hold serial_out (do not emit D[0]).
    • If LOAD=0: serial_out <= SR[0]; SR <= {1'b0, SR[3:1]} (zero-fill, LSB-first).