Parallel-In Serial-Out Register

Inputs: CLK RST LOAD D[3:0]
Outputs: serial_out

Question

Problem: Parallel-In Serial-Out Register. Solve this hands-on electronics task on EWskills.

Accepted Answer

module piso4 (
    input        CLK,
    input        RST,
    input        LOAD,
    input  [3:0] D,
    output reg   serial_out
);
    reg [3:0] shift_reg;

    always @(posedge CLK or posedge RST) begin
        if (RST) begin
            shift_reg  <= 4'b0000;
            serial_out <= 1'b0;
        end else if (LOAD) begin
            shift_reg  <= D;
            serial_out <= serial_out;           // hold output on load edge
        end else begin
            serial_out <= shift_reg[0];         // emit LSB
            shift_reg  <= {1'b0, shift_reg[3:1]};
        end
    end
endmodule

💡Remember

This “no-repeat LSB” contract holds serial_out during load; the first output bit (LSB) appears on the next rising edge after LOAD=0.
Nonblocking assignments ensure the LSB observed is from the pre-shift value.
Zero-fill makes the stream finite.

88. Parallel-In Serial-Out Register

Requirements