87. 4-bit Bidirectional Shift Register

module shift_reg_bidirectional (
    input        CLK,
    input        RST,
    input        DIR,
    input        serial_in,
    output reg [3:0] Q
);
    always @(posedge CLK or posedge RST) begin
        if (RST)
            Q <= 4'b0000;
        else if (DIR)
            Q <= {Q[2:0], serial_in};
        else
            Q <= {serial_in, Q[3:1]};
    end
endmodule

💡Remember

• DIR selects between two concatenations; the active clock edge performs the move.
• Keep reset highest priority so it overrides shifting.