86. 4-bit Register with Synchronous Reset

module reg4_sync_reset (
    input        CLK,
    input        RST,
    input  [3:0] D,
    output reg [3:0] Q
);
    always @(posedge CLK) begin
        if (RST)
            Q <= 4'b0000;
        else
            Q <= D;
    end
endmodule

💡Remember

• Synchronous reset is sampled at the rising edge; changes between edges do not affect Q until the next edge.
• Put higher-priority controls (reset) first, then data/enable.
• Use nonblocking assignments in sequential logic.