85. 4-bit Register

Design a positive-edge–triggered 4-bit register that captures D[3:0] on each rising edge of CLK and holds the value between edges.

Module: reg4
Ports:
- Inputs:
  - CLK
  - D[3:0]
- Outputs:
  - Q[3:0]
Functional behavior
- On each posedge CLK, load Q <= D.
- Between edges, hold the previous value.
- No reset or enable in this baseline.