36. 4-Input NAND Gate Primitive

module nand4_prim (
    input  a,
    input  b,
    input  c,
    input  d,
    output y
);
    nand g_nand (y, a, b, c, d);
endmodule

💡Remember

NAND is simply the negation of an AND.
The first port is always the output, followed by inputs.
Gate primitives support multiple inputs, and the logic follows the 4-state Verilog truth table.
With unknowns: nand(1,1,1,x) → ~x = x.