How do you plan to solve it?
module nand4_prim ( input wire a, input wire b, input wire c, input wire d, output wire y ); // TODO: instantiate the built-in NAND gate primitive // nand <instance_name> ( <out>, <in1>, <in2>, <in3>, <in4> ); nand uut(y, a,b, c,d ); endmodule