36. 4-Input NAND Gate Primitive

How do you plan to solve it?

// 4-Input NAND Gate using Verilog Primitive
module nand4_prim (
  input  wire a, 
  input  wire b, 
  input  wire c, 
  input  wire d, 
  output wire y
);

  // Instantiate built-in nand primitive
  nand (y, a, b, c, d);

endmodule