61. 7-Segment Display Decoder

module sevenseg_hex (
    input  [3:0] hex,
    output reg [6:0] seg   // {a,b,c,d,e,f,g}, ACTIVE-HIGH
);
    always @* begin
        case (hex)
            4'h0: seg = 7'b1111110; // a b c d e f
            4'h1: seg = 7'b0110000; // b c
            4'h2: seg = 7'b1101101; // a b   d e   g
            4'h3: seg = 7'b1111001; // a b c d     g
            4'h4: seg = 7'b0110011; //   b c     f g
            4'h5: seg = 7'b1011011; // a   c d   f g
            4'h6: seg = 7'b1011111; // a   c d e f g
            4'h7: seg = 7'b1110000; // a b c
            4'h8: seg = 7'b1111111; // a b c d e f g
            4'h9: seg = 7'b1111011; // a b c d   f g
            4'hA: seg = 7'b1110111; // a b c   e f g
            4'hB: seg = 7'b0011111; //     c d e f g  (looks like 'b')
            4'hC: seg = 7'b1001110; // a       d e f
            4'hD: seg = 7'b0111101; //   b c d e   g  (looks like 'd')
            4'hE: seg = 7'b1001111; // a       d e f g
            4'hF: seg = 7'b1000111; // a         e f g
            default: seg = 7'b0000000; // blank
        endcase
    end
endmodule
Alternate solution using look-up table// Bit order: seg[6:0] = {a,b,c,d,e,f,g}, ACTIVE-HIGH
module sevenseg_hex (
    input  [3:0] hex,
    output [6:0] seg
);
    // Pack 16 entries × 7 bits = 112-bit constant.
    // Concatenation is MSB..LSB, so put 0xF first and 0x0 last;
    // then select with seg = LUT[hex*7 +: 7] (entry 0 lives at bits [6:0]).
    localparam [7*16-1:0] SEG_LUT = {
        7'b1000111, // F
        7'b1001111, // E
        7'b0111101, // D (looks like 'd')
        7'b1001110, // C
        7'b0011111, // B (lowercase 'b' on 7-seg)
        7'b1110111, // A
        7'b1111011, // 9
        7'b1111111, // 8
        7'b1110000, // 7
        7'b1011111, // 6
        7'b1011011, // 5
        7'b0110011, // 4
        7'b1111001, // 3
        7'b1101101, // 2
        7'b0110000, // 1
        7'b1111110  // 0
    };

    // Variable indexed part-select:
    // pick 7 bits starting at offset (hex*7).
    wire [6:0] seg_lut = SEG_LUT[hex*7 +: 7];

    assign seg = seg_lut;  // active-high drive
endmodule
💡Remember
Bit order matters. We use {a,b,c,d,e,f,g}. Some boards wire {g,f,e,d,c,b,a}—adjust mapping if needed.
Indexed part-select SEG_LUT[hex*7 +: 7] selects 7 bits starting at bit hex*7. Works in Icarus with -g2005. No SystemVerilog needed.
Concatenation order matters In a wide localparam like localparam [7*16-1:0] SEG_LUT = {F, E, D, …, 1, 0}; the leftmost item lands at the MSBs. Put 0 last so entry 0 sits at bits [6:0], making hex*7 +: 7 map naturally (entry i → bits [7*i +: 7]).
Combinational, synthesizable ROM A constant localparam + variable slice synthesizes to a tiny ROM/mux network. No latches, no clocks.
Width-safe & readable Declare the LUT as [7*16-1:0] so the width matches exactly. Using expressions (7*16) is legal and self-documenting.
Unknowns propagate (good for TBs) If hex carries x/z, the index becomes x and seg turns X. That helps catch uninitialized or illegal inputs during simulation.

Please login to run the code.

Testbench Code

`timescale 1ns/1ps

module tb_sevenseg_hex;
    // 1) Inputs
    reg  [3:0] hex;

    // 2) DUT outputs
    wire [6:0] seg;      // ACTIVE-HIGH, {a,b,c,d,e,f,g}

    // 3) Expected (compute with a mirrored case here in TB)
    reg  [6:0] expected_seg;  // ACTIVE-HIGH expected

    // 4) Single mismatch flag (case-inequality catches X/Z)
    wire mismatch = (seg !== expected_seg);

    // Accounting
    integer TOTAL_TEST_CASES        = 0;
    integer TOTAL_PASSED_TEST_CASES = 0;
    integer TOTAL_FAILED_TEST_CASES = 0;

    // Limits
    integer VCD_MAX_CASES   = 32; // normal printed rows
    integer ERROR_MAX_CASES = 32; // error printed rows
    integer printed_rows    = 0;
    integer printed_errors  = 0;

    // DUT
    sevenseg_hex dut(.hex(hex), .seg(seg));

    // VCD dump
    initial begin
        $dumpfile("tb_sevenseg_hex.vcd");
        $dumpvars(0,
            tb_sevenseg_hex.hex,
            tb_sevenseg_hex.seg,
            tb_sevenseg_hex.expected_seg,
            tb_sevenseg_hex.mismatch
        );
        $dumpon;
    end

    // Golden computation (ACTIVE-HIGH) – matches the DUT table
    always @* begin
        case (hex)
            4'h0: expected_seg = 7'b1111110;
            4'h1: expected_seg = 7'b0110000;
            4'h2: expected_seg = 7'b1101101;
            4'h3: expected_seg = 7'b1111001;
            4'h4: expected_seg = 7'b0110011;
            4'h5: expected_seg = 7'b1011011;
            4'h6: expected_seg = 7'b1011111;
            4'h7: expected_seg = 7'b1110000;
            4'h8: expected_seg = 7'b1111111;
            4'h9: expected_seg = 7'b1111011;
            4'hA: expected_seg = 7'b1110111;
            4'hB: expected_seg = 7'b0011111;
            4'hC: expected_seg = 7'b1001110;
            4'hD: expected_seg = 7'b0111101;
            4'hE: expected_seg = 7'b1001111;
            4'hF: expected_seg = 7'b1000111;
            default: expected_seg = 7'b0000000;
        endcase
    end

    // Header + init
    initial begin
        hex = 4'h0;
        $display(" hex |  seg   | expected | mismatch   (seg bit order {a,b,c,d,e,f,g})");
        $display("---------------------------------------------------------------------");
    end

    // Apply + check (drive -> wait -> read combinational mismatch)
    task apply_and_check;
        input [3:0] th;
        begin
            hex = th;
            #1; // settle

            TOTAL_TEST_CASES = TOTAL_TEST_CASES + 1;
            if (!mismatch) begin
                TOTAL_PASSED_TEST_CASES = TOTAL_PASSED_TEST_CASES + 1;
                if (printed_rows < VCD_MAX_CASES) begin
                    $display("  %1x  | %07b |  %07b |    %0d",
                             hex, seg, expected_seg, mismatch);
                    printed_rows = printed_rows + 1;
                end
            end else begin
                TOTAL_FAILED_TEST_CASES = TOTAL_FAILED_TEST_CASES + 1;
                if (printed_errors < ERROR_MAX_CASES) begin
                    $display("ERR: hex=%1x => seg=%07b (expected %07b)",
                             hex, seg, expected_seg);
                    printed_errors = printed_errors + 1;
                end
            end

            if (TOTAL_TEST_CASES == VCD_MAX_CASES) $dumpoff; // optional VCD cap
        end
    endtask

    integer i;
    initial begin
        // Exhaustive 0..F
        for (i = 0; i < 16; i = i + 1) apply_and_check(i[3:0]);

        // Summary
        $display("---------------------------------------------------------------------");
        $display("TOTAL_TEST_CASES=%0d", TOTAL_TEST_CASES);
        $display("TOTAL_PASSED_TEST_CASES=%0d", TOTAL_PASSED_TEST_CASES);
        $display("TOTAL_FAILED_TEST_CASES=%0d", TOTAL_FAILED_TEST_CASES);
        $display("ALL_TEST_CASES_PASSED=%s", (TOTAL_FAILED_TEST_CASES==0) ? "true" : "false");
        #2 $finish;
    end
endmodule