How do you plan to solve it?
/*Write your code here*/
module sevenseg_hex(
input [3:0] hex,
output [6:0] seg
);
reg [6:0] temp;
always@* begin
case(hex)
4'h0 : temp = 7'b1111110;
4'h1 : temp = 7'b0110000;
4'h2 : temp = 7'b1101101;
4'h3 : temp = 7'b1111001;
4'h4 : temp = 7'b0110011;
4'h5 : temp = 7'b1011011;
4'h6 : temp = 7'b1011111;
4'h7 : temp = 7'b1110000;
4'h8 : temp = 7'b1111111;
4'h9 : temp = 7'b1111011;
4'hA : temp = 7'b1110111;
4'hB : temp = 7'b0011111;
4'hC : temp = 7'b1001110 ;
4'hD : temp = 7'b0111101;
4'hE : temp = 7'b1001111;
4'hF : temp = 7'b1000111;
endcase
end
assign seg = temp;
endmodule