How do you plan to solve it?
/*Write your code here*/
module sevenseg_hex (input [3:0]hex,
output reg [6:0]seg);
always @(*) begin
case (hex)
4'b0000: begin
seg=7'b1111110;
end
4'b0001: begin
seg=7'b0110000;
end
4'b0010: begin
seg=7'b1101101;
end
5'b0011: begin
seg=7'b1111001;
end
5'b0100: begin
seg=7'b0110011;
end
5'b0101: begin
seg=7'b1011011;
end
4'b0110: begin
seg=7'b1011111;
end
4'b0111: begin
seg=7'b1110000;
end
4'b1000: begin
seg=7'b1111111;
end
4'b1001: begin
seg=7'b1111011;
end
4'b1010: begin
seg=7'b1110111;
end
4'b1011: begin
seg=7'b0011111;
end
4'b1100: begin
seg=7'b1001110;
end
4'b1101: begin
seg=7'b0111101;
end
4'b1110: begin
seg=7'b1001111;
end
4'b1111: begin
seg=7'b1000111;
end
default: seg=7'b0000000;
endcase
end
endmodule