7. Controlled Buffer/Inverter Synthesis

Design a combinational logic circuit for a reconfigurable signal controller. The system must process a single data input (Data In) and provide a controlled output (Data Out) based on the state of a configuration control signal (Config). The circuit must function as a non-inverting buffer when Config is 0 and as an inverter when Config is 1.

Constraints

  • You must utilize two input sources: Data In and Config.
  • The Data Out must be equal to Data In when Config = 0, and the inverse of Data In when Config = 1.
  • To adhere to system architecture requirements, the logic must be synthesized using only XNOR gate components.
  • You are strictly forbidden from using standard AND, OR, NAND, NOR, XOR, or NOT gate components.

Behavioral Reference

ConfigData InData Out
000
011
101
110