Equality Comparator Synthesis

Question

Problem: Equality Comparator Synthesis. Solve this hands-on electronics task on EWskills.

Accepted Answer

Output Equations

The logic is derived by identifying that a match occurs when the XOR operation yields 0, which is then inverted.

Combined Expression: Equality Output = ((A1 XOR B1) XOR 1) AND ((A0 XOR B0) XOR 1)

Calculation Breakdown

Bitwise Comparison (A XOR B): The XOR gate acts as an inequality detector. It outputs 0 only if the two bits are identical.
Inversion (X XOR 1): Since you are restricted to using only XOR gates, an XOR gate with one input tied to logic HIGH acts as a controlled inverter.
Synthesis: By inverting the disparity results and combining them through the final AND logic, the output will only be HIGH (1) when both bit comparisons resulted in a "match" (a 0 at the first XOR stage).

Circuit Implementation

Bitwise Comparison: Route A1, B1 to an XOR gate, and A0, B0 to a second XOR gate.
Logic Processing: Utilize additional XOR gates tied to logic HIGH to invert these results, ensuring we capture the "match" state for each bit pair.
Final Synthesis: Route the outputs of the inverting XOR gates into an AND gate to verify that both bit pairs match simultaneously.
Connect: Map the output of the AND gate to the Equality Output probe.

A1	A0	B1	B0	Equality Output
0	0	0	0	1
0	1	0	1	1
1	0	1	0	1
1	1	1	1	1
Any other combination	-	-	-	0

6. Equality Comparator Synthesis