94. Custom PWM Generator

Duty register: Four D flip-flops store DUTY. LOAD_DUTY selects new data or feedback.

D_duty_reg[i] = LOAD_DUTY · DUTY[i] + LOAD_DUTY' · Q_duty_reg[i]
Where i = 0,1,2,3.

MOD-8 counter: A synchronous 3-bit T-flip-flop counter advances only while RUN_EN = 1.

T0 = RUN_EN
T1 = RUN_EN · Q0
T2 = RUN_EN · Q0 · Q1
COF = Q2 · Q1 · Q0
COF' = (Q2 · Q1 · Q0)'

PWM controller: A positive-edge JK flip-flop starts immediately and keeps RUN_EN active until the current cycle reaches count 111.

J = RUN
K = RUN' · COF = (RUN + COF')'
Q = RUN_EN
Active-low CLR = START

Duty loading: Load while idle or at the end of an active cycle. This prevents mid-cycle glitches.

LOAD_DUTY = START · (COF + RUN_EN')
          = START · (COF' · RUN_EN)'

Comparator: Compare registered duty Q_duty_reg[3:0] with B = {0, Q2, Q1, Q0}. The output of comparator (A < B) is an active-LOW output.

PWM_OUT is HIGH while the counter value is less than the stored duty.

PWM_OUT = RUN_EN · (A < B)'
        = RUN_EN · (Counter < Registered_Duty)

Saturation: For DUTY above 1000, A[3:0] is greater than every counter value from 0000 to 0111, so PWM_OUT remains HIGH for all eight counts.