77. D Flip-Flop

Design a positive-edge–triggered D flip-flop that captures D on each rising edge of CLK and holds the value until the next rising edge.

Requirements

• Module: dff_posedge
• Ports:
  • Inputs:
    • CLK
    • D
  • Outputs:
    • Q
• Functional behavior
  • On each rising edge of CLK, Q takes D.
  • Between rising edges, Q holds its value.
  • No reset or enable in this baseline.
• Modeling constraints
  • Use always @(posedge CLK) with nonblocking assignment <=.