76. D Latch with Enable-Synchronous Reset

Design a level-sensitive D latch with an enable and a reset that is honored only while the latch is transparent (EN=1).

Requirements

• Module: d_latch_en_sync_reset
• Ports:
  • Inputs:
    • EN
    • RST
    • D
  • Outputs:
    • Q
• Functional behavior
  • EN=1, RST=1 → Q=0
  • EN=1, RST=0 → Q=D
  • EN=0 → Q holds previous value
• Modeling constraints
  • Infer a level-sensitive latch using always @(EN or RST or D).
  • Apply reset logic only inside the EN branch.
  • Use nonblocking assignments (<=) for storage.

Behaviour / Worked Example

From Q=0:

1. EN=1,RST=1,D=1 → Q=0
2. EN=1,RST=0,D=1 → Q=1
3. EN=0,RST=1,D=0 → Q=1
4. EN=0,RST=0,D=1 → Q=1
5. EN=1,RST=1,D=0 → Q=0
6. EN=1,RST=0,D=0 → Q=0