78. D Flip-Flop with Asynchronous Reset

Design a positive-edge–triggered D flip-flop with an active-high asynchronous reset. When RST=1, the output clears to 0 immediately; otherwise, Q captures D on each rising edge of CLK.

Requirements

• Module: dff_async_reset
• Ports:
  • Inputs:
    • CLK
    • RST
    • D
  • Outputs:
    • Q
• Functional behavior
  • RST=1 → Q=0 immediately.
  • On posedge CLK with RST=0 → Q=D.
  • Between events → hold.
• Modeling constraints
  • Use always @(posedge CLK or posedge RST) with nonblocking assignments (<=).
  • Reset has priority over data capture.