76. D Latch with Enable-Synchronous Reset

Behavioral (recommended)

module d_latch_en_sync_reset (
    input  EN,
    input  RST,
    input  D,
    output reg Q
);
    always @(EN or RST or D) begin
        if (EN) begin
            if (RST) Q <= 1'b0;
            else     Q <= D;
        end else begin
            Q <= Q;
        end
    end
endmodule

💡Remember

• Level-sensitive latch is inferred via incomplete assignment in the hold path.
• Reset is honored only while EN=1.
• Nonblocking assignments (<=) express storage semantics.
• No power-up value is assumed; drive an initial vector in the testbench.

Data-flow (mux feedback)

module d_latch_en_sync_reset (
    input  EN,
    input  RST,
    input  D,
    output Q
);
    wire d_sel = RST ? 1'b0 : D;
    assign Q = EN ? d_sel : Q;
endmodule

💡Remember

• Expresses Q = EN ? (RST ? 0 : D) : Q.
• Functionally identical; some tools warn on feedback nets.
• Preferred style for synthesis is the behavioral model.