75. D Latch

Behavioral (recommended)

module d_latch (
    input  EN,
    input  D,
    output reg Q
);
    always @(EN or D) begin
        if (EN)
            Q <= D;      // track D when enabled
    end
endmodule

💡Remember

• Level-sensitive storage is inferred by leaving the hold path unassigned (or using an explicit self-assignment).
• While EN=1, any glitch on D can pass to Q; drive or filter D appropriately.
• Using nonblocking (<=) communicates sequential intent and avoids racey read-before-write issues.
• Power-up state is unspecified without reset; drive an initial vector in the testbench.

Dataflow

module d_latch (
    input  EN,
    input  D,
    output Q
);
    // Mux with feedback: Q = EN ? D : Q
    assign Q = (EN) ? D : Q;
endmodule

💡Remember

• This expresses the latch as a feedback mux.
• Some tools warn on the explicit feedback loop; prefer the behavioral style for clean synthesis.
• Functional behavior matches the behavioral model: transparent on EN=1, hold on EN=0.