80. DFF with Async Reset and Preset

Design a positive-edge–triggered D flip-flop with active-high asynchronous reset and preset. Reset dominates preset; preset forces Q=1 only when reset is inactive.

Requirements

• Module: dff_async_reset_preset
• Ports:
  • Inputs:
    • CLK
    • RST
    • PRE
    • D
  • Outputs:
    • Q
• Functional behavior (priority)
  • RST=1 → Q=0
  • else PRE=1 → Q=1
  • else on posedge CLK → Q=D
  • otherwise hold