79. DFF with Synchronous Reset

Design a positive-edge–triggered D flip-flop in which reset is sampled on the rising edge. When RST=1 at the clock edge, the output clears to 0; otherwise, it captures D.

Requirements

• Module: dff_sync_reset
• Ports:
  • Inputs:
    • CLK
    • RST
    • D
  • Outputs:
    • Q
• Functional behavior
  • On posedge CLK with RST=1 → Q=0
  • On posedge CLK with RST=0 → Q=D
  • Between edges → hold
• Modeling constraints
  • Reset has priority over data.
  • Use nonblocking assignments (<=).