80. DFF with Async Reset and Preset

module dff_async_reset_preset (
    input  CLK,
    input  RST,
    input  PRE,
    input  D,
    output reg Q
);
    always @(posedge CLK or posedge RST or posedge PRE) begin
        if (RST)
            Q <= 1'b0;
        else if (PRE)
            Q <= 1'b1;
        else
            Q <= D;
    end
endmodule

💡Remember

• Put all asynchronous controls in the sensitivity list and encode the priority explicitly (RST over PRE over data).
• While an async control is asserted, clock edges do not change Q.
• Use nonblocking assignments inside the clock/reset block.
• In real designs, deassert async controls cleanly (often synchronized) to avoid hazards.