69. DFF with Async Reset and Preset

module dff_async_reset_preset (
    input  CLK,
    input  RST,
    input  PRE,
    input  D,
    output reg Q
);
    always @(posedge CLK or posedge RST or posedge PRE) begin
        if (RST)
            Q <= 1'b0;
        else if (PRE)
            Q <= 1'b1;
        else
            Q <= D;
    end
endmodule
💡RememberPut all asynchronous controls in the sensitivity list and encode the priority explicitly (RST over PRE over data).
While an async control is asserted, clock edges do not change Q.
Use nonblocking assignments inside the clock/reset block.
In real designs, deassert async controls cleanly (often synchronized) to avoid hazards.

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Testbench Code

`timescale 1ns/1ps

module tb_dff_async_reset_preset;
    // 1) Inputs
    reg CLK, RST, PRE, D;
    // 2) Outputs
    wire Q;
    // 3) Expected outputs (prefixed "expected_")
    reg  expected_Q;
    // 4) Mismatch (HIGH when outputs != expected)
    wire mismatch;

    // DUT
    dff_async_reset_preset dut(.CLK(CLK), .RST(RST), .PRE(PRE), .D(D), .Q(Q));

    // Scoreboard mirrors DUT behavior exactly
    always @(posedge CLK or posedge RST or posedge PRE) begin
        if (RST)      expected_Q <= 1'b0;
        else if (PRE) expected_Q <= 1'b1;
        else          expected_Q <= D;
    end

    assign mismatch = (Q !== expected_Q);

    // Counters / limits
    integer TOTAL_TEST_CASES        = 0;
    integer TOTAL_PASSED_TEST_CASES = 0;
    integer TOTAL_FAILED_TEST_CASES = 0;
    integer VCD_MAX_CASES           = 32;
    integer ERROR_MAX_CASES         = 32;

    integer i, j;

    // Free-running clock (10 time-unit period)
    initial begin
        CLK = 1'b0;
        forever #5 CLK = ~CLK;
    end

    // VCD — Inputs -> Outputs -> Expected -> mismatch; start at #0
    initial begin
        $dumpfile("tb_dff_async_reset_preset.vcd");
        $dumpvars(0,
            tb_dff_async_reset_preset.CLK,
            tb_dff_async_reset_preset.RST,
            tb_dff_async_reset_preset.PRE,
            tb_dff_async_reset_preset.D,
            tb_dff_async_reset_preset.Q,
            tb_dff_async_reset_preset.expected_Q,
            tb_dff_async_reset_preset.mismatch
        );
        $dumpon;
    end

    task log_case;
    begin
        TOTAL_TEST_CASES = TOTAL_TEST_CASES + 1;
        if (!mismatch) begin
            TOTAL_PASSED_TEST_CASES = TOTAL_PASSED_TEST_CASES + 1;
        end else begin
            TOTAL_FAILED_TEST_CASES = TOTAL_FAILED_TEST_CASES + 1;
            if (TOTAL_FAILED_TEST_CASES <= ERROR_MAX_CASES)
                $display("[FAIL] CLK=%b RST=%b PRE=%b D=%b  Q=%b expected_Q=%b  t=%0t",
                         CLK, RST, PRE, D, Q, expected_Q, $time);
        end
        if (TOTAL_TEST_CASES == VCD_MAX_CASES) $dumpoff;
    end
    endtask

    // Asynchronous controls
    task async_assert_reset;  begin RST = 1'b1; PRE = 1'b0; #1; log_case(); end endtask
    task async_release_reset; begin RST = 1'b0;             #1; log_case(); end endtask
    task async_assert_preset; begin PRE = 1'b1; RST = 1'b0; #1; log_case(); end endtask
    task async_release_preset;begin PRE = 1'b0;             #1; log_case(); end endtask

    // Drive D on negedge; check after next posedge
    task capture_cycle;
        input d_val;
    begin
        @(negedge CLK);
        D = d_val;
        @(posedge CLK);
        #1;
        log_case();
    end
    endtask

    initial begin
        // Start with unknown expected to reflect flop power-up
        D = 1'b0; RST = 1'b0; PRE = 1'b0; expected_Q = 1'bx;
        @(negedge CLK);

        // Directed: basic reset / preset and captures
        async_assert_reset();
        async_release_reset();
        capture_cycle(1'b1);
        capture_cycle(1'b0);

        async_assert_preset();
        async_release_preset();
        capture_cycle(1'b0);

        // Simultaneous asserts: reset must dominate preset
        RST = 1'b0; PRE = 1'b0; #1;
        RST = 1'b1; PRE = 1'b1; #1; log_case();   // both high -> Q must be 0
        async_release_reset();                     // keep PRE=1
        async_release_preset();

        // More captures
        capture_cycle(1'b1);
        capture_cycle(1'b0);

        // Randomized sequences
        for (i=0; i<6; i=i+1) begin
            if ($random) async_assert_reset(); else async_release_reset();
            if ($random) async_assert_preset(); else async_release_preset();
            capture_cycle($random);
        end

        // Summary
        $display("TOTAL_TEST_CASES=%0d",        TOTAL_TEST_CASES);
        $display("TOTAL_PASSED_TEST_CASES=%0d", TOTAL_PASSED_TEST_CASES);
        $display("TOTAL_FAILED_TEST_CASES=%0d", TOTAL_FAILED_TEST_CASES);
        $display("ALL_TEST_CASES_PASSED=%s",    (TOTAL_FAILED_TEST_CASES==0) ? "true" : "false");

        #2 $finish;
    end
endmodule