20. Equality Comparator Synthesis

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A 2-bit equality comparator asserts its output only when both pairs of corresponding bits match perfectly. Because standard NOT gates are prohibited, XOR gates with one input tied to a logic high (1) are used as controlled inverters to track the equality of each bit pair. The inverted results are then combined using an AND gate.

Boolean Equation:

Equality Output = ((A1 ⊕ B1) ⊕ 1) · ((A0 ⊕ B0) ⊕ 1)