74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output reg Q,
    output reg Qn
);
	// Write your code here
	always@(*)begin
    if(EN)begin
        case({S,R})
          2'b00 : {Q,Qn} = {Q,Qn};
          2'b01 : {Q,Qn} = {1'b0,1'b1};
          2'b10 : {Q,Qn} = {1'b1,1'b0};
          2'b11 : {Q,Qn} = {1'b0,1'b1};
        endcase
    end
    else 
       {Q,Qn} = {Q,Qn};
    end
endmodule