74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output reg Q,
    output reg Qn
);
always @(*)begin
    if(EN) begin
        if(S == 0 && R == 0)begin
            Q <= Q ;
            Qn <= ~Q ;
        end   
        if(S == 1 && R == 0)begin
            Q <= 1 ;
            Qn <= ~Q ;
        end
        if(S == 0 && R == 1)begin
            Q <= 0 ;
            Qn <= ~Q ;
        end 
        if(S == 1 && R == 1)begin
            Q <= 0 ;
            Qn <= ~Q ;
        end
    end  
    else begin
        Q <= Q;
        Qn <= ~Q;
    end     

end
endmodule