74. Gated SR Latch

Wrap the SR logic in an if (EN) case

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output reg Q,
    output reg Qn
);
	// Write your code here
        always @* begin
            if (EN) begin
                case ({S, R})
                    2'b10: begin Q = 1; Qn = 0; end   
                    2'b01: begin Q = 0; Qn = 1; end   
                    2'b00: ;                          
                    2'b11: begin Q = 1'b0; Qn = 1'b1; end 
                endcase
            end
        end
endmodule